The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a structure and method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor integrated circuit.
In many mixed signal or high frequency RF applications, both high performance, high-speed capacitors and inductors are utilized. Low series resistance, low loss, high Q and low (RC) time constants are characteristic of such components in high frequency applications for achieving high performance. In addition, these device structures are fabricated by processes compatible with CMOS processing (e.g., using AlCu alloys to pure copper in dual damascene structures).
In particular, a metal-insulator-metal (MIM) capacitor is commonly used in high performance applications in CMOS technology. Typically, the MIM capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from Al or AlCu alloys that are patterned and etched through the use of several photolithography photomasking steps. The thin insulating dielectric layer is typically made from silicon oxide or silicon nitride, deposited by chemical vapor deposition (CVD), for example.
Damascene processing is a common method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning the dielectric layer using photolithography and reactive ion etching (RIE), and then filling the formed recesses with conductive metal. The excess metal is then removed by chemical mechanical polishing (CMP), leaving the troughs or channels filled with metal. For example, damascene wiring lines may be used to form bit lines in DRAM devices, with processing similar to the formation of tungsten (W) studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners (underlying diffusion barriers) are coated with chemical vapor deposited (CVD) W metal, then polished back to the oxide.
In a dual damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film, followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness may be slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud (via) recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes. Next, the stud/wire metallization is deposited, and then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional single damascene processing. Moreover, with a dual damascene process, two layers of metal are formed simultaneously (e.g., a wiring line and contact stud vias), thus avoiding an interface therebetween.
In the fabrication of semiconductor devices, metal lines are often embedded in dielectric layers in a multilevel structure, particularly in the latter stages (referred to as “back end of the line” or “BEOL”) of the fabrication process. However, with the continued scaling of semiconductor technologies, narrower linewidths are accompanied by features shrinking in the direction perpendicular to the wafer. For example, in BEOL structures, vias and wires become shorter so that they can be patterned with thinner resists to achieve narrower linewidths. As the space between two successive line levels becomes smaller, devices such as MIM capacitors (which fit in between two wiring levels), become more difficult to fabricate since there is less headroom therebetween. In addition, existing schemes for forming MIM capacitors are dependent on successfully landing vias at different heights (e.g., on the top plate, the bottom plate and the prior level Cu wire) with a single via reactive ion etch (RIE) step.
In technologies such as CMOS 9SF, a MIM capacitor is placed between formed at about twice the thickness (2×) of the thinnest wiring level(s). In this case, the via landing on the top plate lands about 3000 angstroms (Å) above the via on the Cu wire underneath. This leads to a requirement of extreme selectivity of the RIE process to the top plate material. Eventually, in future 11SF technology, a situation will be reached in which the conventional MIM capacitor structure can no longer be placed between 2× thickness wires, since the via height therebetween is now less than the MIM capacitor stack height.
One way to address this situation would be to implement a single mask scheme, wherein a dielectric followed by the top-plate metal is deposited directly over the copper. A single mask is then used to pattern the top-plate. With this approach, the resulting stack height would be less with respect to a conventional configuration, since there is no need to include either the isolation barrier or the bottom plate in the MIM capacitor stack. In other words, the bottom plate of the MIM capacitor becomes part of the Cu wiring level itself. Unfortunately, the direct exposure of dielectric to copper means that oxide materials cannot be used as the capacitor dielectric material (as it would attack the copper), thus ruling out the very attractive high-K materials for capacitor dielectrics.
Furthermore, using a damascene copper plate places an upper limit on the size of the plate, additionally compromising the surface quality and planarity of the Cu electrode (due dishing, scratches, etc., following CMP). Moreover, for existing MIM capacitor integration schemes in which the top plate is placed in the interlevel dielectric (ILD) and has a different height via landing thereupon, an extremely selective via RIE process is needed to prevent etching through the top plate and resulting in yield or reliability problems. The edge of the top plate of the MIM capacitor is a weak point in these integration schemes because the top plate RIE endpoints in the underlying dielectric, leading to RIE damage, microtrenching and local thinning of the dielectric.
Accordingly it would be desirable to be able to flexibly integrate a MIM capacitor between BEOL wiring levels for semiconductors devices with decreasing vertical heights, and in a manner that does not undesirably limit the choice of MIM capacitor dielectrics.